Physical Designer

Job Details

Job Type:
Full Time
Job Experience:
3 year
Posted On:
2017/06/19
No. of Vacancies:
1
Location(s):
Expected Salary:
300000
Key Skills:
DRC, Timing Closure, Static Timing Analysis, Floor Planning, Physical Verification, LVS, Placement, STA, Design

Job Description

Job Description

 

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·        Power planning, optimization, power grid andsignal routing considering timing constraints. 

·        Design floor planning, analogue and memorymacro placement. 

·        Place and route including timing closure.

·        Extraction of layout parasitics and SPEF/ SDFgeneration. Signal integrity tests. 

·        Post-synthesis static timing analysis (STA)and post-layout STA.

·        Physical verification (DRC, ERC, LVS, ANTENNArules). 

·        Writing, running, optimization of scripts forabove tasks. 

·        Implement and monitor Quality Assurance/ QualityControl standards based on corporate guidelines in a project setting. 

·        Have done multiple tape outs and provenrecord of designing complex ICs in state of the art CMOS process technologiesand has successfully placed products into volume production, preferablymultiple times.

Desired Candidate Profile

·        At least 3-5 years professional experience inmicroelectronics physical implementation. 

·        Good verbal and writing communication skills.Fabrication process variation impacts and performance. 

·        Experience in low-power designtechniques. 

·        Good understanding of ERC, EMI rules andimpact on final chip verification and cycle time reduction. 

·        Ability to work in a team environment andparticipate in cross-functional activities. 

·        Experience with the following tools: 

·        Mandatory: Cadence RTL Compiler,SOC-Encounter/ EDIS, ETS, EPS. o 

·        Desirable: Mentor Calibre/ Assura.

Company Profile:

Quess CorpLtd (Magna Infotech)

Magna Infotech Pvt Ltd

Recruiter Name:HR

Contact Company:Quess Corp Ltd (Magna Infotech)

Email Address:sriram.a@magna.in